Exemplary embodiments of the present invention relate to semiconductor designing technology, and more particularly, to a semiconductor integrated circuit.
Semiconductor integrated circuit packaging technology continues to advance for meeting demands for smaller chip sizes and packaging reliability. As electrical/electronic devices with improved performance characteristics are miniaturized, diverse stack packaging technologies have been developed.
“Stack” means a pile of two or more chips or packages in a vertical direction in the semiconductor industry. By using a stack package, a semiconductor memory device may achieve a memory capacity twice as much as a memory capacity achieved through a conventional semiconductor integration process. Since the stack packages have benefits in terms of packaging density and packaging area efficiency, the research and development of stack packages are being actively pursued.
Stack packages may be fabricated through a method of stacking individual semiconductor chips and packaging the entire stacked semiconductor chips or a method of stacking packaged individual semiconductor chips. The individual semiconductor chips of a stack package are electrically connected to each other through metal wire or through silicon via (TSV). In particular, a stack package using a through silicon via has a structure where a through silicon via is formed internally within semiconductor chips and the semiconductor chips are physically and electrically connected in a vertical direction by the through silicon via.
FIG. 1A is a plan view illustrating a semiconductor integrated circuit according to a first embodiment of a prior art. FIG. 1B is a side cross-sectional view of the semiconductor integrated circuit of FIG. 1A along a line A-A′. FIG. 2A is a plan view illustrating a semiconductor integrated circuit according to a second embodiment of a prior art. FIG. 2B is a side cross-sectional view of the semiconductor integrated circuit of FIG. 1A along a line B-B′.
Referring to FIGS. 1A to 2B, an example where there is one semiconductor chip and one through silicon via penetrating the semiconductor chip vertically will be described for illustration purposes.
Referring to FIGS. 1A and 1B, a semiconductor chip 10 includes a through silicon via 12 penetrating the semiconductor chip in a vertical direction. The semiconductor chip 10 is generally a silicon substrate into which a P-type impurity such as boron (B) is ion-implanted, where the implanted substrate is used as a P-well. Although not illustrated in the drawings, a well-biasing region may be formed to apply a well bias of a low voltage VSS to the semiconductor chip 10. The through silicon via 12 is formed of a metal having a great conductivity. For example, the through silicon via 12 may be formed of copper (Cu).
Referring to FIGS. 2A and 2B, a semiconductor chip 20 is used as a P-well, and the semiconductor chip 20 includes a through silicon via 22 penetrating, for example, completely, through the semiconductor chip 20 in a vertical direction, and an N-well 24 includes the through silicon via 22. Herein, the semiconductor chip 20 may be a silicon substrate into which a P-type impurity, such as boron (B), is ion-implanted. As for the through silicon via 22, a metal having a great conductivity such as copper (Cu) may be used. Also, the N-well 24 is a region formed of an N-type impurity as opposed to the P-type impurity of the substrate. Meanwhile, although not illustrated in the drawings, the semiconductor chip 20 includes a well biasing region for applying a well bias of a low voltage VSS, and the N-well 24 includes a well biasing region for applying a well bias of a high voltage VDD as well.
At least two or more semiconductor chips 10 or 20 may be stacked, where they interface signals and power source with each other through the through silicon vias 12 or 22, respectively.
The above-described semiconductor integrated circuit, however, raises the following concerns.
Referring back to FIGS. 1A and 1B, a metal-semiconductor junction is formed between the semiconductor chip 10 and the through silicon via 12. As a result, a parasitic diode called Schottky barrier diode is formed between the semiconductor chip 10 and the through silicon via 12. Therefore, a backward bias is designed to be normally applied across the Schottky barrier diode between the semiconductor chip 10 and the through silicon via 12. In short, although the ground voltage VSS, which is the lowest voltage, flows to the through silicon via 12, a forward bias across the Schottky barrier diode may be prevented by applying a well bias of a ground voltage VSS to the semiconductor chip 10. Here, since the through silicon via 12 is formed in the semiconductor chip 10, the total area of the semiconductor chip 10 decreases, and the resistance of the semiconductor chip 10 increases. This is because when the semiconductor chip 10 operates as a resistor, its resistance is in reverse proportion to a cross sectional area of the semiconductor chip 10. When the resistance of the semiconductor chip 10 is increased, the bias voltage in being applied across the semiconductor chip 10 tends to be subjected to an increase.
Likewise, in case of FIGS. 2A and 2B, although the power source voltage VDD, which is the highest voltage, is applied at the through silicon via 22, a forward bias across the Schottky barrier diode may be prevented by applying a well bias of the power source voltage VDD to the N-well 24. However, since the through silicon via 22 is formed to penetrate the N-well 24, for example, completely, the resistance of the N-well 24 becomes greater as described above. As a result, the bias voltage level applied through the N-well 24 may decrease.
As a result, a forward bias across the respective Schottky barrier diodes formed between the semiconductor chip 10 and the through silicon via 12 and formed between the N-well 24 and the through silicon via 22 may develop and form a current path. Even when an amount of current flowing through the current path is minute, power is still being wasted, signal transmission speeds decrease, and noise in signals increase. When excessively great current flows through the current path, a latch up phenomenon may occur and cause a failure in the semiconductor chips 10 or 20.
To address the above-described concerns with the conventional technology, when the through silicon via 12 and 22 are formed in the semiconductor chip 10 or 20 through the N-well 24, an insulation layer may be formed with more than a predetermined thickness, or an ion-implantation may be performed. In performing these steps, however, the total number of procedural steps increases and, the production time and production cost for fabricating a semiconductor integrated circuit increase.